AWS Quantum Technologies Blog A framework for quantum-classical integration decisions This post was contributed by Dimitar Trenev, Sebastian Stern, Tyler Takeshita, Cedric Lin, Peter Komar, Pooja Rao, Jerome Gonthier, and Elica Kyoseva. As quantum computing matures toward fault tolerance, a pressing question faces the high-performance computing (HPC) community: why is tightly integrating quantum processors to classical supercomputing infrastructure important? Today, algorithm researchers from Amazon Web Services (AWS), Lawrence Berkeley National Laboratory (LBNL), National Aeronautics and Space Administration (NASA), and NVIDIA published a performance model for hybrid quantum-classical workflows that evaluates whether a given hybrid workload is accelerated by low-latency integration of quantum and classical resources, or if standard network connectivity is sufficient. Two levels, two different answers Discussions about quantum-classical connectivity often conflate two fundamentally different concerns: the need for low-level real-time control of quantum hardware, and the need for communication requirements at the application level. Our paper separates them explicitly into two levels. The real-time level primarily refers to the control and calibration tasks as well as quantum error correction (QEC), where classical decoders process error syndromes and apply corrections and calibration tasks needed to keep quantum processors performing correctly. The decoder and control stack must keep pace with the syndrome-extraction cycle and react fast enough that the correction latency does not exceed the logical gate cycle (microseconds for superconducting devices); low-latency coupling here is non-negotiable. The application level is where hybrid algorithms, such as variational solvers and quantum-enhanced sampling, perform the computation by repeatedly exchanging data between a classical host and a quantum processing unit (QPU). Current approaches to hybrid algorithms do not generally rely on classical processing completing within a device-imposed timescale — either the workflow exchanges data only between circuit executions (today’s noisy intermediate-scale quantum, or NISQ, algorithms), or a fault-tolerant logical QPU hides the real-time