IonQ Inc. researchers have achieved a nearly three-fold increase in the speed of measuring commuting logical operators using a new approach to quantum low-density parity-check (LDPC) codes. The work addresses a key bottleneck in fault-tolerant quantum computation by streamlining operations on logical qubits within the same encoded block. The key ingredient is a scheduler code determining the measurement sequence and allowing for the decoding of all logical measurement outcomes. Numerical simulations with the LDPC codes Q70 and Q102 show a speed-up of nearly 3× over Viterbi measurements for the measurement of commuting logical operators. Combining these fast logical measurements with a new variant of the CliNR partial error correction scheme enables a speed-up of up to 74× for random Clifford circuits. This approach also applies to non-Clifford gates, producing a speed-up of up to 5× for Toffoli gates. For each logical measurement, a new code is formed, merging the memory with the resource state. The exact protocol is easy to understand by inspecting the circuit without additional formalism. Quantum LDPC Codes and Logical Qubit Encoding A significant advance in fault-tolerant quantum computation has been achieved through a novel approach to logical qubit encoding. Unlike the substantial qubit overhead of surface codes, LDPC codes encode multiple logical qubits within the same physical block, a characteristic that previously presented challenges to operational speed. This work directly addresses that bottleneck. By utilizing only cat states, each interacting with the memory for a single time step before measurement, this new technique circumvents previous limitations requiring complex resource states. Numerical simulations using LDPC codes Q70 and Q102 of the walking cat architecture revealed a nearly 3× speed-up over Viterbi measurements for the measurement of commuting logical operators. The approach extends to non-Clifford gates, achieving up to a 5× speed-up for Toffoli gates. The success with