New post-quantum chip architecture passes key milestone in 28nm test environment BTQ Technologies and ITRI have validated a compute-in-memory chip architecture designed to accelerate post-quantum cryptography. Read Next: New hydrogen engine achieves diesel-level performance for medium-duty vehicles Canada-based BTQ Technologies and the Industrial Technology Research Institute (ITRI) have completed the first milestone in a multi-year program to validate a new chip architecture designed to accelerate post-quantum cryptography. The Quantum Compute-in-Memory (QCIM) architecture is being developed as part of a broader chip roadmap led by BTQ and ICTK. The technology is intended to provide hardware-based cryptographic acceleration for devices and systems that will need protection against future quantum computers. The companies say the results could support future applications across military systems, industrial equipment, automotive technology, IoT devices, Physical AI and connected infrastructure. Architecture validated in 28-nanometre environment The first phase of the collaboration focused on validating the QCIM core under demanding operating conditions. The architecture was tested within a TSMC 28-nanometre design environment, where researchers evaluated its ability to accelerate cryptographic operations while maintaining functional correctness. More from Innovation See All The tests covered algorithms associated with FIPS 203, 204 and 205, which form part of NIST’s emerging post-quantum cryptography standards. The architecture is also being designed to support additional algorithms as security requirements and standards evolve. BTQ describes QCIM as a soft IP cryptographic accelerator capable of supporting both conventional and post-quantum cryptographic functions in a compact, low-power design. The key concept is to perform cryptographic operations inside the memory subsystem rather than moving data between separate processing and memory components. This approach is intended to reduce data movement, latency and power consumption. Furthermore, the architecture is also designed to be “crypto-agile,” allowing it to support different cryptographic algorithms as requirements change. From post-quantum algorithms to real-world hardware The development